Stacking silicon

A technique which will allow silicon wafers to be stacked accurately and inexpensively in 3D structures has been developed by researchers at the University of Southampton.

According to Dr Michael Kraft at the University's School of Electronics & Computer Science (ECS), the major challenge when stacking silicon wafers is to align one wafer to another, matching all the features.

'The alignment needs to be accurate,' commented Dr Kraft. 'At the moment, big chunky machines are being used and the process is being carried out optically. The optical path is long and this introduces errors.'

Dr Kraft and his colleague, Professor Mark Spearing at the School of Engineering Sciences, worked with Dr Liudi Jiang, who is now a Roberts Fellow in the School of Engineering Sciences, to develop what they describe as 'an effective passive alignment technique for the achievement of nanoprecision alignment'.

The approach adopted by the researchers means that the alignment features consisting of convex pyramids and concave pits can be fabricated and chip scale specimens can be successfully bonded after the microfabrication process. An alignment precision of 200 nanometres has been achieved.