Tilera Corporation has launched its TILE64 processor, the first in a family of Tile Processor chips based on an architecture that, it claims, can scale to hundreds and even thousands of cores.
The TILE64 processor contains 64 full-featured, programmable cores – each capable of running Linux. Initial target markets for the processor include the embedded networking and digital multimedia markets.
Tilera was founded to bring to market the MIT research of Dr. Anant Agarwal who first created the mesh-based multicore architecture in 1996. The “Raw” project received multi-million dollar DARPA and National Science Foundation grants and spawned the development of the first tiled multicore processor prototype and associated multicore software in 2002.
The company has a dozen customers who are currently integrating the TILE64 processor into products for advanced networking and digital multimedia applications.
Tilera’s new architecture eliminates the on-chip bus interconnect, a kind of centralized intersection that information must flow through between cores within a chip, or before it leaves the chip. As engineers have added more cores to chips, the bus has created an information traffic jam because packets from these cores all must travel to one central point, like a spoke-and-wheel traffic intersection in an old city.
The technology eliminates the bus by placing a communications switch on each processor core and arranging them in a grid fashion on the chip. This creates a 2-dimensional traffic system for packets.
Tilera’s implementation of this grid architecture is called iMesh (intelligent Mesh), and it incorporates a number of patented innovations that enhance the performance and flexibility of the mesh. Because the aggregate bandwidth is orders of magnitude greater than a bus and the distance between cores is shorter, the iMesh technology can be leveraged to create grids as large or small as an application requires, creating what it calls a “computing-by-the-yard” scalability.
Each of the 64 cores on the TILE64 processor is capable of running its own operating system. Each core is a full-featured, general-purpose processor that includes L1 and L2 caches, as well as a distributed L3 cache. The cores are overlaid with the iMesh network, which provides low-latency, high bandwidth communications between the cores, memory and the I/O.
In order to minimise total system power, cost and real estate, the TILE64 processor integrates four DDR2 memory controllers and a complete array of high speed I/O interfaces, including two 10 Gbps XAUI, two 10 Gbps PCIe, two 1 Gbps Ethernet RGMII, and a programmable flexible I/O interface to support interfaces such as compact flash and disk drives.
The Tilera Multicore Development Environment (MDE) includes an Eclipse-based Integrated Development Environment (IDE), an ANSI standard C compiler, a full-system simulation model and a set of flexible command-line interfaces. The MDE also provides graphically-driven tools for debugging and profiling multicore processors, and an application level library that provides lightweight socket-like stream communication mechanisms.
The TILE64 processor is available now in three different device variants based on frequency and I/O capabilities. Production pricing for the TILE64 family starts at $435 in 10K unit quantities. Tilera’s roadmap also includes plans for a 36-core and a 120-core device.
More detail on the architecture of the device can be found here.