Hardware performance counters used to protect microgrids from cyberattacks

Researchers at King Abdullah University of Science and Technology (KAUST) are using hardware performance counters to protect microgrids from cyberattacks.

Small-scale renewable energy systems can be vulnerable to cyberattacks. A team of KAUST researchers has devised a method to protect this critical infrastructure using low-cost hardware-based malware detection mechanisms
Small-scale renewable energy systems can be vulnerable to cyberattacks. A team of KAUST researchers has devised a method to protect this critical infrastructure using low-cost hardware-based malware detection mechanisms - © 2022 KAUST; Heno Hwang

Microgrids are small ‘power islands’ that provide electricity for services including healthcare, food and water during emergencies. According to KAUST, the relative simplicity and isolation of microgrids makes them attractive targets for cyberattacks aimed at disrupting communities.

Hardware performance counters (HPCs) are special registers embedded within most computers to monitor events, such as how many times a certain command has been performed.

“HPCs were originally used for profiling purposes or to identify bottlenecks within code,” said Ioannis Zografopoulos, who conducted the research with Charalambos Konstantinou at KAUST and colleagues from the University of Texas at Dallas. “However, we have utilised HPCs to detect code patterns that indicate the execution of malicious code on our devices: specifically, the embedded controllers of solar inverters that convert the output of solar photovoltaic panels into usable power for consumers.”

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Zografopoulos and co-workers developed tailor-made HPCs that were able to monitor the commands occurring within the inverters, without interfering in their main job of converting solar energy to electricity. Crucially, the team added an extra layer of security by including time series classifiers; these are algorithms that correlate potentially malicious combinations of commands with the time sequence of HPC firing events.

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